1. Field of the Invention
The present invention relates to an insulated gate semiconductor device such as an insulated gate bipolar transistor (hereinafter referred to as an IGBT) and a method of fabricating the same. More particularly, the invention relates to an improvement in short-circuit tolerance.
2. Description of the Background Art
&lt;1. Structure of Conventional Device&gt;
FIG. 40 is a plan view of a conventional N-channel IGBT 100. The IGBT 100 comprises a multiplicity of IGBT elements (hereinafter referred to as IGBT unit cells) 110 connected in parallel, only one of which is illustrated. An emitter electrode 7 and an oxide film 8 to be described later with reference to FIG. 41 are not illustrated in FIG. 40. The configurations of various mask patterns to be used in the process steps for fabricating the IGBT 100 are also shown in FIG. 40. FIGS. 41 and 42 are cross-sectional views of one of the IGBT unit cells 110 taken along the lines A--A and B--B of FIG. 40, respectively. A circuit diagram of an equivalent circuit of the IGBT unit cell 110 is also illustrated in FIG. 41.
Referring to FIGS. 41 and 42, the IGBT unit cell 110 includes a p-type collector layer 1 which is a p-type semiconductor substrate and an n-type epitaxial layer 2. The layers 1 and 2 form a semiconductor body 120. A p-type base region 3 is formed in a partial region in the top major surface of the n-type epitaxial layer 2 of the semiconductor body 120 by selective diffusion of p-type impurities. In a partial region in the top major surface of the semiconductor body 120 are also formed n-type emitter regions 4 by selective diffusion of n-type impurities. A gate insulating film 5 is formed to cover the top surface of the p-type base region 3 between the top surface of the n-type epitaxial layer 2 and the top major surface of the n-type emitter regions 4. The gate insulating films 5 for adjacent IGBT unit cells 110 are integrally formed on the top surface of the n-type epitaxial layer 2. A gate electrode 6 made of, for example, polycrystalline silicon (hereinafter referred to as polysilicon) is formed on the gate insulating film 5. The emitter electrode 7 made of, for example, aluminum is formed such that it is electrically connected to both the p-type base region 3 and the n-type emitter regions 4. The gate electrode 6 and the emitter electrode 7 are insulated from each other by an oxide film 8 serving as an inter-layer insulating film, and are electrically connected in common in and between all of the IGBT unit cells 110. A high-concentration p-type semiconductor region 31 is formed in the p-type base region 3 through diffusion of p-type impurities at high concentration in a pattern which surrounds the n-type emitter regions 4. A collector electrode 9 made of metal is formed on the bottom major surface of the p-type collector layer 1 integrally for all of the IGBT unit cells 110.
As shown in FIG. 40, the IGBT cell 110 has regions in which the n-type emitter regions 4 are relatively wide as viewed from the top and regions in which they are relatively narrow. The region around the line A--A is one of the former regions while the region around the line B--B is one of the latter regions. The dotted lines of FIG. 40 represent a mask pattern 51 to be used for formation of the gate electrode 6, a mask pattern 52 to be used for formation of the high-concentration p-type semiconductor region 31, and a mask pattern 53 to be used for formation of the n-type emitter regions 4 in a process of fabricating the IGBT 100.
&lt;2. Operation of Conventional Device&gt;
Referring to FIG. 41, the IGBT unit cell 110 includes an insulated gate field effect transistor MOS, which may be a metal-oxide-semiconductor transistor and is hereinafter referred to as an MOSFET, a pnp bipolar transistor Tr1, an npn bipolar transistor Tr2, and a resistance Rb. These elements are equivalently connected to each other as shown in the equivalent circuit diagram FIG. 41.
When a gate voltage V.sub.GE is applied across the gate and emitter electrodes 6 and 7 with a collector voltage V.sub.CE applied across the collector and emitter electrodes 9 and 7, the p-type semiconductor in the top surface of the p-type base region 3 between the n-type emitter regions 4 and n-type epitaxial layer 2 is inverted into an n-type semiconductor to form n-type channels. Then conduction is permitted between the n-type epitaxial layer 2 serving as a drain of the MOSFET and the n-type emitter regions 4 serving as a source thereof, and an electronic current flows from the n-type emitter regions 4 through the n-type channels into the n-type epitaxial layer 2. The electronic current serves as a base current for the transistor Tr1. In response to the electronic current, holes are introduced from the p-type collector layer 1 into the n-type epitaxial layer 2. Some of the introduced holes are recombined with the carrier electrons in the n-type epitaxial layer 2, and the other holes flow through the p-type base region 3 into the emitter electrode 7 to provide a hole current. As a result, the IGBT 100 conducts or turns on, that is, conduction is permitted across the collector and emitter electrodes 9 and 7.
The IGBT 100, a voltage-controlled transistor having insulated gates (MOS gates) like the MOSFET, is advantageous in that a drive circuit of the IGBT 100 is constructed more simply than that of bipolar transistors and in that a collector-emitter saturation voltage (ON-voltage) lower than that of the MOSFET is achieved. The latter advantage is provided because the holes introduced from the p-type collector layer 1 into the n-type epitaxial layer 2 cause a conductivity modulation so that the resistance of the n-type epitaxial layer 2 effectively becomes low.
When the gate voltage V.sub.GE is a zero voltage or is zero-biased or when it is a negative voltage or is negatively biased, the MOSFET enters a cut-off state so that the electronic current slops flowing. As a result, the IGBT 100 is cut off. However, accumulated holes remain in the n-type epitaxial layer 2 during the transition period in which the transition from ON to OFF starts. A certain period of time (turn-off time) is required for the holes accumulated in the course of the transition to disappear. During the turn-off period, the hole current continues flowing while decaying. The accumulated holes are useful for achieving a low saturation voltage when the IGBT 100 is on but are a factor prolonging the turn-off time when the IGBT 100 turns off. Hence the amount of holes to be introduced in the ON-state or the lifetime thereof should be optimized.
The IGBT unit cell 110 includes a parasitic thyristor formed by the n-type emitter regions 4, the p-type base region 3, the n-type epitaxial layer 2 and the p-type collector layer 1. The parasitic effect which is turn-on of the parasitic thyristor associated with the operation of the IGBT 100 sometimes prevents the original function of the IGBT 100. It is therefore necessary to suppress the parasitic effect. One of the effective approaches for suppression of the parasitic effect is to decrease the lateral resistance Rb of a part of the p-type base region 3 which lies just under the n-type emitter regions 4. For decrease in the resistance Rb, there has been proposed an arrangement shown in FIGS. 41 and 42 in which the high-concentration p-type semiconductor region 31 is provided just under the n-type emitter regions 4, which is disclosed in Japanese Patent Application Laid-Open No. 60-196974 (1985), for example. As illustrated in FIGS. 41 and 42, the high-concentration p-type semiconductor region 31 is formed on the inside of the n-type emitter regions 4 for the purpose of exerting no influence on a gate threshold voltage. That is, the high-concentration p-type semiconductor region 31 is formed such that the region 31 itself is not included in the n-type channels to be formed in the p-type base region 3 when the gate voltage V.sub.GE is applied.
&lt;3. Disadvantage of Conventional Device&gt;
The IGBT 100 is often used for an inverter device and the like. It is hence necessary that the IGBT 100 is not broken down when the inverter device is short-circuited or when the IGBT 100 turns on with a short-circuit voltage applied thereto. The resistance to short-circuit of the IGBT 100 (short-circuit tolerance) decreases in proportion to the product of the voltage and the current when the IGBT 100 is short-circuited and a short-circuit time. The IGBT 100 having a small chip area, in particular, has a low short-circuit tolerance.
The voltage at the time of short-circuit and the short-circuit time are determined by the conditions under which the IGBT 100 is used, e.g., the operating conditions of the inverter. Since the IGBT 100, when short-circuited, is saturated, the current at the time of the short-circuit is just a saturation current I.sub.CE (sat) of the IGBT 100. The establishment of a low saturation current I.sub.CE (sat) is effective for improving the short-circuit tolerance. The saturation current I.sub.CE (sat) is determined by: ##EQU1## where:
.alpha.pnp is a current transfer ratio of the pnp transistor;
C.sub.ox is a gate capacitance;
.mu.n is a surface mobility;
W is a channel width;
L is a channel length;
V.sub.GE is the gate voltage; and
V.sub.GE (th) is the gate threshold voltage.
For reduction in losses where the IGBT 100 is applied as a switching clement to the inverter and the like, a small collector-emitter saturation voltage V.sub.CE (sat) is required. One of the effective schemes to decrease a collector-emitter saturation voltage V.sub.CE (sat) is to improve the electrical characteristics of a portion corresponding to the MOSFET (the portion MOS of FIG. 41) in the IGBT unit cell 110 to reduce a drop voltage when the MOS is conducting. For example, a shallow diffusion is carried out in a diffusing step for forming the p-type base region 3 to shorten the channel length L of the MOS. Otherwise, the IGBT unit cell 110 is reduced in size and increased in density by reducing the width of the p-type base region 3 (the whole lateral width of the p-type base region 3 of FIGS. 41, 42), to thereby relatively increase the total of the channel widths W for the whole IGBT 100.
However, either shortening the channel length L or increasing the channel width W for reduction in collector-emitter saturation voltage V.sub.CE (sat) is accompanied by increase in saturation current I.sub.CE (sat) as will be understood from Formula (1). Then the parasitic thyristor causes latch-up to break down the IGBT 100, or otherwise the product of the voltage and current at the time of short-circuit grows large, so that the short-circuit tolerance falls off. The conventional IGBT 100 is, therefore, disadvantageous in that low losses when used as a switching clement cannot coexist with high short-circuit tolerance.